1. Field of the Invention
The present invention relates to frequency synthesizers capable of operating at high frequencies. More particularly, the present invention pertains to a frequency divider circuit for use in conjunction with a voltage-controlled oscillator in a frequency synthesizer.
2. Description of the Related Art
Frequency synthesizers are essential components of communication receivers. Most known frequency synthesizers include two primary circuits: a voltage controlled oscillator (VCO), and a prescaler which is typically configured from a frequency divider circuit. The two circuits (VCO and frequency divider) are connected within a phase-locked loop arrangement. Known frequency divider circuits are shown in FIGS. 1 and 2. As depicted in FIG. 1, a simple frequency divider circuit is implemented by a plurality of series-connected invertors I1, I2 and I3. A clock signal (CK) having a particular frequency is applied to inventor I1 and the complement of the clock signal CK (pronounced CK BAR and referred to hereinafter as "CKB") is applied to inventor 13 for producing an output signal having a frequency substantially half of CK, i.e. CK/2. The clock signals CK and CKB are commonly applied, as shown in FIG. 2, to a gate terminal of a MOSFET transistor that is connected in series with a corresponding inventor.
The drawbacks of the frequency divider circuits of FIGS. 1 and 2 is that the inventor switching speeds are limited. In other words, the speed at which the state of the inventor can change is limited, thus rendering a frequency synthesizer incorporating the frequency divider circuit unacceptable for high frequency use, i.e., for use with high frequency clock signals.